HAFDAL Workshop '24

March 3rd 2024

Edinburgh, Scotland

The 1st Workshop on Hardware Acceleration of Functional and Declarative Languages (HAFDAL '24) will be co-located with HPCA, at the EICC in Edinburgh on March 3rd 2024.

This workshop brings together computer architects and programming language implementers to identify software/hardware co-designs of high level execution models.

Workshop Programme

A major challenge with the practical deployment of Internet-of-Things (IoTs) is how to develop the high-quality code needed in order to produce robust and secure IoT devices. In other domains, high-level programming languages have shown to be efficient vehicles towards this. However, the very limited compute power provided by IoT devices have made it difficult to apply the same approach to IoT devices. The Cephalopode processor is an attempt at implementing a low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks like garbage collection, arbitrary precision arithmetic, process management and scheduling, etc. into dedicated hardware, the Cephalopode processor explore the hypothesis that high-level functional languages can be used even for low-power IoT devices.

The talk will provide an overview of the Cephalopode project, including stops at the input language, the compiler, the processor architecture, the tool environment we created to design the processor, as well as some early results on the practicality of the approach.

When running quantum circuits on a quantum computer, we're dealing with a world with very different capabilities to the classical one in which they were generated. For example, the famous "No-cloning Theorem" means that arbitrary values cannot be copied. If these differences aren't respected, it can lead to very costly runtime errors.

In this talk, I will present BRAT: a functional programming language for writing programs which interleave quantum and classical execution, and quantum resource limitations are enforced by the type system. Moreover, programs in the two worlds are united by a compositional syntax, thanks to their affinities for monoidal structure.

This talk is a look back on work published at ISMM 2020, on how the language features and data structures typical in OCaml conspire to have interesting memory-system performance effects that result in different optimisation strategies in both hardware and software from imperative languages. I will discuss the unique design patterns for software prefetching that can be used to alleviate these, the reasons for different parts of the modern microarchitecture stack reacting unusually to the code and with varying levels of success, the factors that matter for other languages, and ways forward for both next-generation hardware and software.

This talk presents PipelineC, an open source project which sits between traditional register transfer language (RTL) and high-level synthesis (HLS). PipelineC aims to make hardware design accessible to domain specialists with basic programming skills by using C-like syntax. Major features include: timing feedback from synthesis and place and route (PnR) tools that drives automatic pipelining of combinatorial logic, as well as derived finite state machines and global point to point wires/clock crossings for composing complex designs outside of feedforward dataflow function call syntax.

Clash is a functional hardware description language, but it’s also just a combination of a regular Haskell library with type and function definitions for circuit design and a compiler that translates Haskell programs to digital circuits.

There are many ways a Haskell program can be interpreted as a circuit description, where the Clash project picks a particular one. Even more broadly, the Clash project is one of many approaches to "circuit design using a functional/declarative language". This talk will explore some of those options, how the Clash approach compares to them: what has worked well for Clash and in what aspects other options will most likely always be better.

Implementations of general purpose functional languages overwhelmingly target CPUs. This choice is despite the semantic gap between their high-level execution model and CPU assembly. Meanwhile, advances in FPGAs continue to improve the density of custom hardware resources offered to wide audiences. We consider this a call to reinvestigate hardware implementations of functional languages. We present “Heron”, a special purpose processor core for pure, non-strict functional languages. This talk recaps Heron's reduction core, compares its performance to a variety of stock CPU implementations, and presents work towards its concurrent hardware garbage collector.

In complex living organisms, the nervous system is the part that detects environmental changes and internal anomalies that impact them, by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. In the Nervous Systems project we envisage a reconfigurable self-aware electronic system with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous fault tolerance.

Building your first silicon prototype can be a significant effort. There is always more work that you could do before your tapeout deadline and so balancing risk with opportunity is key. By exploiting open-source infrastructure (in our team's case, OpenPiton) and making long term decisions, you can build chips with increasing capabilities. In this talk I will share our team's experience on the design side (rather than backend) that can make tapeouts more achievable.

Workshop registration includes lunch, coffee and access to industry tutorials in the morning. Registration is £150 (£120 for IEEE/ACM members), £110 for students (£90 for members). Register on the main HPCA website.

Workshop Scope

The 1960s and 1970s saw LISP machines for supporting AI workloads. The 1980s saw graph reductions machines for functional language workloads. After a 30 year lull, modern hardware technology has attracted renewed interest in hardware acceleration of high level languages. This workshop brings together computer architects and programming language implementers to identify software/hardware co-designs of these high level execution models.

We invite two forms of participation: (1) submissions for 30 minute talks, (2) 5-10 minute lightning talks about related projects and early results. Please send an abstract to craig.ramsay@hw.ac.uk by November 20th. We are looking for submissions that cover the motivation, design, or real-world application of hardware technology for functional/declarative languages, their compilers and runtime systems. The work should target truly custom (e.g. ASIC/FPGA) hardware, or exploit modern hardware features for functional/declarative language implementation, across the design space of:

  • Special-purpose processor architectures for functional or declarative languages.
  • Automatic, high-level synthesis of custom accelerators from plain, high-level software functions.
  • Hardware description languages embedded in, or hosted by, high-level software languages.


  • February 2024 - A full lineup of HAFLDAL'24 speakers is confirmed.
  • October 2023 - Christiaan Baaij (QBayLogic) and Carl-Johan Seger (Chalmers University) confirmed as invited speakers.
  • October 2023 - Our call for participation is now open. Please email inquiries concerning submission to: craig.ramsay@hw.ac.uk
  • September 2023 - The inaugural HAFDAL workshop proposal has been accepted. Stay tuned for further updates and submission guidelines.

Programme Committee

Robert Stewart Heriot-Watt University Associate Professor (Co-chair)
Craig Ramsay Heriot-Watt University Research Associate (Co-chair)
Christiaan Baaij QBayLogic Co-Founder
Jonathan Balkind UC Santa Barbara Assistant Professor
Kevin Hammond IOHK Head of Engineering
Matthew Naylor University of Cambridge Senior Research Associate
Rachit Nigam Cornell University PhD Candidate
Jocelyn Sérot L'université Clermont Auvergne Professor
Mary Sheeran Chalmers University Professor
Satnam Singh Groq Fellow
Phil Trinder University of Glasgow Professor

Rob Stewart and Craig Ramsay are the co-general and programme Chairs.
This workshop will be supported by the HAFLANG project (EPSRC funded; EP/W009447/1).