Hardware Acceleration of Functional Languages

This project will develop a special purpose processor for accelerating functional programming languages, by implementing functional languages runtime components in hardware using the latest FPGA technology.


The latest updates about HAFLANG.

  • October 2022 - We visited our industry partner QBayLogic in Enschede, Netherlands.
  • June 2022 - Craig Ramsay has been appointed to the postdoc position. The project starts July 2022.
  • November 2021 - The project will start in May 2022.
  • November 2021 - There is funding available for PhD projects with this project. Send inquiries to Rob Stewart.
  • November 2021 - EPSRC confirms funding for this 3 year project.

Project goals

By implementing functional languages in FPGA hardware, this project aims to increase throughput to shorten runtimes and reduce energy use compared with CPUs. Our objectives are:

  • Remove compiler-based IR translations, typical of software implementations of functional languages targeting CPUs, by designing a processor architecture that better matches the graph reduction model.
  • Investigate memory hierarchy design best suited for non-strict functional languages.
  • Develop graph reduction innovations in hardware, such as garbage collection "close to" intelligent memory units.
  • Discover the kinds of applications best suited for hardware acceleration of graph reduction.

For inquiries about the project, and the postdoc position and funded PhD projects, please contact the PI Dr. Rob Stewart at R.Stewart@hw.ac.uk.