Hardware Acceleration of Functional Languages
This project will develop a special purpose processor for accelerating functional programming languages, by implementing functional languages runtime components in hardware using the latest FPGA technology.
News
The latest updates about HAFLANG.
- October 2024 - Craig Ramsay gave seminar about Heron, our graph reduction processor, at Chalmers University of Technology..
- September 2024 - Yukang Xie joins the project as a PhD student.
- September 2024 - our Haskell Symposium 2024 paper about Cloaca, our hardware-based garbage collector, is online.
- June 2024 - our IFL 2023 paper about Heron, our graph reduction hardware core, is online.
- March 2024 - the video recordings and slides of talks from our HAFDAL workshop are online.
- February 2024 - Our paper "Heron: Modern Hardware Graph Reduction" has been conditionally accepted to IFL 2023.
- December 2023 - Craig Ramsay presented our Heron processor architecture at the Centre for Electronics Frontiers at the University of Edinburgh.
- November 2023 - Craig Ramsay presented our latest results and future plans to the Dependable Systems Group at Heriot-Watt University. It is on YouTube.
- September 2023 - Our HAFDAL workshop will be co-located with HPCA '24 in Edinburgh, March 2024. A call-for-participation will be published shortly.
- June 2023 - We curated a history of functional architectures.
- May 2023 - A new mailing list has been set up "Computer Architectures for Functional Programming languages". People are encouraged to subscribe!
- October 2022 - We visited our industry partner QBayLogic in Enschede, Netherlands.
- June 2022 - Craig Ramsay has been appointed to the postdoc position. The project starts July 2022.
- November 2021 - The project will start in May 2022.
- November 2021 - There is funding available for PhD projects with this project. Send inquiries to Rob Stewart.
- November 2021 - EPSRC confirms funding for this 3 year project.
Project goals
By implementing functional languages in FPGA hardware, this project aims to increase throughput to shorten runtimes and reduce energy use compared with CPUs. Our objectives are:
- Remove compiler-based IR translations, typical of software implementations of functional languages targeting CPUs, by designing a processor architecture that better matches the graph reduction model.
- Investigate memory hierarchy design best suited for non-strict functional languages.
- Develop graph reduction innovations in hardware, such as garbage collection "close to" intelligent memory units.
- Discover the kinds of applications best suited for hardware acceleration of graph reduction.
For inquiries about the project and funded PhD projects, please contact the PI Dr. Rob Stewart at R.Stewart@hw.ac.uk.